Electrostatic discharge (ESD) is a continuing problem in the design, manufacture, and utilization of integrated circuits. A major source of ESD exposure to integrated circuits is from the human body (described by the “Human Body Model”, HBM). In this situation, a packaged integrated circuit acquires a charge when it is touched by a human who is electrostatically charged (e.g. From walking across a carpet). A charge of about 0.4 uC may be induced on a body capacitance of 100 pF, for example, leading to an electrostatic potential of 4 kV or more and discharge peak currents of several amperes to the integrated circuit for longer than 100 ns. A second source of ESD exposure is from charged metallic objects (described by the “Machine Model”, MM), which is characterized by a greater capacitance, lower internal resistance and transients that have significantly higher peak current levels than a HBM ESD source. A third source of ESD exposure is due to the discharge of stored charge on the integrated circuit itself (described by the “Charged Device Model”, CDM), to ground with rise times of less than 500 ps. For all three sources of ESD exposure, both positive and negative polarity discharges may occur.
As silicon technologies scale, transistor safe-operating area is reduced causing ESD protection requirements to become more stringent. The increased requirements are causing the die area for the ESD circuits to increase. The increased die area drives up cost and increased parasitic capacitance from the ESD protection circuit results in increased functional degradation of the integrated circuit. It is therefore desirable to provide adequate ESD protection while at the same time reducing ESD circuit area and also reducing the impact of the ESD circuit upon the integrated circuit performance.